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cpuid.h
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1 /* This file is part of the Vc library.
2 
3  Copyright (C) 2009-2012 Matthias Kretz <kretz@kde.org>
4 
5  Vc is free software: you can redistribute it and/or modify
6  it under the terms of the GNU Lesser General Public License as
7  published by the Free Software Foundation, either version 3 of
8  the License, or (at your option) any later version.
9 
10  Vc is distributed in the hope that it will be useful, but
11  WITHOUT ANY WARRANTY; without even the implied warranty of
12  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13  GNU Lesser General Public License for more details.
14 
15  You should have received a copy of the GNU Lesser General Public
16  License along with Vc. If not, see <http://www.gnu.org/licenses/>.
17 
18 */
19 
20 #ifndef CPUID_H
21 #define CPUID_H
22 
23 namespace ROOT {
24 namespace Vc
25 {
26 
27 /**
28  * \ingroup Utilities
29  * \headerfile cpuid.h <Vc/cpuid.h>
30  *
31  * This class is available for x86 / AMD64 systems to read and interpret information about the CPU's
32  * capabilities.
33  *
34  * Before any of the getter functions may be called, the init() function must have been called. It
35  * will be called automatically, but for any function executing before main, you better call
36  * \c CpuId::init() first.
37  *
38  * %Vc users will most likely not need this class directly, but rely on the
39  * isImplementationSupported, bestImplementationSupported, extraInstructionsSupported, and
40  * currentImplementationSupported functions.
41  */
42 class CpuId
43 {
44  typedef unsigned char uchar;
45  typedef unsigned short ushort;
46  typedef unsigned int uint;
47 
48  public:
54  };
55 
56  /**
57  * Reads the CPU capabilities and stores them for faster subsequent access.
58  *
59  * Will be executed automatically before main, but not necessarily before other functions
60  * executing before main.
61  */
62  static void init();
63 
64  //! Return the cache line size in bits.
65  static inline ushort cacheLineSize() { return static_cast<ushort>(s_cacheLineSize) * 8u; }
66  //! Return the ProcessorType.
67  static inline ProcessorType processorType() { return s_processorType; }
68  //! Return the family number of the processor (vendor dependent).
69  static inline uint processorFamily() { return s_processorFamily; }
70  //! Return the model number of the processor (vendor dependent).
71  static inline uint processorModel() { return s_processorModel; }
72  //! Return the number of logical processors.
73  static inline uint logicalProcessors() { return s_logicalProcessors; }
74  //! Return whether the CPU vendor is AMD.
75  static inline bool isAmd () { return s_ecx0 == 0x444D4163; }
76  //! Return whether the CPU vendor is Intel.
77  static inline bool isIntel () { return s_ecx0 == 0x6C65746E; }
78  //! Return whether the CPU supports SSE3.
79  static inline bool hasSse3 () { return s_processorFeaturesC & (1 << 0); }
80  //! Return whether the CPU supports the PCLMULQDQ instruction.
81  static inline bool hasPclmulqdq() { return (s_processorFeaturesC & (1 << 1)) != 0; }
82  //! Return whether the CPU supports the MONITOR/MWAIT instructions.
83  static inline bool hasMonitor() { return (s_processorFeaturesC & (1 << 3)) != 0; }
84  //! Return whether the CPU supports the Virtual Machine Extensions.
85  static inline bool hasVmx () { return (s_processorFeaturesC & (1 << 5)) != 0; }
86  //! Return whether the CPU supports the Safer Mode Extensions.
87  static inline bool hasSmx () { return (s_processorFeaturesC & (1 << 6)) != 0; }
88  //! Return whether the CPU supports the Enhanced Intel SpeedStep technology.
89  static inline bool hasEist () { return (s_processorFeaturesC & (1 << 7)) != 0; }
90  //! Return whether the CPU supports Thermal Monitor 2.
91  static inline bool hasTm2 () { return (s_processorFeaturesC & (1 << 8)) != 0; }
92  //! Return whether the CPU supports SSSE3.
93  static inline bool hasSsse3() { return (s_processorFeaturesC & (1 << 9)) != 0; }
94  //! Return whether the CPU supports FMA extensions using YMM state.
95  static inline bool hasFma () { return (s_processorFeaturesC & (1 << 12)) != 0; }
96  //! Return whether the CPU supports CMPXCHG16B.
97  static inline bool hasCmpXchg16b() { return (s_processorFeaturesC & (1 << 13)) != 0; }
98  //! Return whether the CPU supports the Perfmon and Debug Capability.
99  static inline bool hasPdcm () { return (s_processorFeaturesC & (1 << 15)) != 0; }
100  //! Return whether the CPU supports Direct Cache Access: prefetch data from a memory mapped device.
101  static inline bool hasDca() { return (s_processorFeaturesC & (1 << 18)) != 0; }
102  //! Return whether the CPU supports SSE 4.1
103  static inline bool hasSse41() { return (s_processorFeaturesC & (1 << 19)) != 0; }
104  //! Return whether the CPU supports SSE 4.2
105  static inline bool hasSse42() { return (s_processorFeaturesC & (1 << 20)) != 0; }
106  //! Return whether the CPU supports the MOVBE instruction.
107  static inline bool hasMovbe() { return (s_processorFeaturesC & (1 << 22)) != 0; }
108  //! Return whether the CPU supports the POPCNT instruction.
109  static inline bool hasPopcnt(){ return (s_processorFeaturesC & (1 << 23)) != 0; }
110  //static inline bool hasTscDeadline() { return (s_processorFeaturesC & (1 << 24)) != 0; }
111  //! Return whether the CPU supports the AESNI instructions.
112  static inline bool hasAes () { return (s_processorFeaturesC & (1 << 25)) != 0; }
113  //static inline bool hasXsave() { return (s_processorFeaturesC & (1 << 26)) != 0; }
114  //! Return whether the CPU and OS support the XSETBV/XGETBV instructions.
115  static inline bool hasOsxsave() { return (s_processorFeaturesC & (1 << 27)) != 0; }
116  //! Return whether the CPU supports AVX.
117  static inline bool hasAvx () { return (s_processorFeaturesC & (1 << 28)) != 0; }
118  //! Return whether the CPU supports 16-bit floating-point conversion instructions.
119  static inline bool hasF16c () { return (s_processorFeaturesC & (1 << 29)) != 0; }
120  //! Return whether the CPU supports the RDRAND instruction.
121  static inline bool hasRdrand(){ return (s_processorFeaturesC & (1 << 30)) != 0; }
122  //! Return whether the CPU contains an x87 FPU.
123  static inline bool hasFpu () { return (s_processorFeaturesD & (1 << 0)) != 0; }
124  static inline bool hasVme () { return (s_processorFeaturesD & (1 << 1)) != 0; }
125  //! Return whether the CPU contains Debugging Extensions.
126  static inline bool hasDe () { return (s_processorFeaturesD & (1 << 2)) != 0; }
127  //! Return whether the CPU contains Page Size Extensions.
128  static inline bool hasPse () { return (s_processorFeaturesD & (1 << 3)) != 0; }
129  //! Return whether the CPU supports the RDTSC instruction.
130  static inline bool hasTsc () { return (s_processorFeaturesD & (1 << 4)) != 0; }
131  //! Return whether the CPU supports the Model Specific Registers instructions.
132  static inline bool hasMsr () { return (s_processorFeaturesD & (1 << 5)) != 0; }
133  //! Return whether the CPU supports the Physical Address Extension.
134  static inline bool hasPae () { return (s_processorFeaturesD & (1 << 6)) != 0; }
135  //! Return whether the CPU supports the CMPXCHG8B instruction.
136  static inline bool hasCx8 () { return (s_processorFeaturesD & (1 << 8)) != 0; }
137  //! Return whether the CPU supports Memory Type Range Registers.
138  static inline bool hasMtrr () { return (s_processorFeaturesD & (1 << 12)) != 0; }
139  //! Return whether the CPU supports CMOV instructions.
140  static inline bool hasCmov () { return (s_processorFeaturesD & (1 << 15)) != 0; }
141  //! Return whether the CPU supports the CLFLUSH instruction.
142  static inline bool hasClfsh() { return (s_processorFeaturesD & (1 << 19)) != 0; }
143  //! Return whether the CPU supports ACPI.
144  static inline bool hasAcpi () { return (s_processorFeaturesD & (1 << 22)) != 0; }
145  //! Return whether the CPU supports MMX.
146  static inline bool hasMmx () { return (s_processorFeaturesD & (1 << 23)) != 0; }
147  //! Return whether the CPU supports SSE.
148  static inline bool hasSse () { return (s_processorFeaturesD & (1 << 25)) != 0; }
149  //! Return whether the CPU supports SSE2.
150  static inline bool hasSse2 () { return (s_processorFeaturesD & (1 << 26)) != 0; }
151  static inline bool hasHtt () { return (s_processorFeaturesD & (1 << 28)) != 0; }
152  //! Return whether the CPU supports SSE4a.
153  static inline bool hasSse4a() { return (s_processorFeatures8C & (1 << 6)) != 0; }
154  //! Return whether the CPU supports misaligned SSE instructions.
155  static inline bool hasMisAlignSse() { return (s_processorFeatures8C & (1 << 7)) != 0; }
156  //! Return whether the CPU supports the AMD prefetchw instruction.
157  static inline bool hasAmdPrefetch() { return (s_processorFeatures8C & (1 << 8)) != 0; }
158  //! Return whether the CPU supports the XOP instructions.
159  static inline bool hasXop () { return (s_processorFeatures8C & (1 << 11)) != 0; }
160  //! Return whether the CPU supports the FMA4 instructions.
161  static inline bool hasFma4 () { return (s_processorFeatures8C & (1 << 16)) != 0; }
162  //! Return whether the CPU supports the RDTSCP instruction.
163  static inline bool hasRdtscp() { return (s_processorFeatures8D & (1 << 27)) != 0; }
164  static inline bool has3DNow() { return (s_processorFeatures8D & (1u << 31)) != 0; }
165  static inline bool has3DNowExt() { return (s_processorFeatures8D & (1 << 30)) != 0; }
166  //! Return the size of the L1 instruction cache.
167  static inline uint L1Instruction() { return s_L1Instruction; }
168  //! Return the size of the L1 data cache.
169  static inline uint L1Data() { return s_L1Data; }
170  //! Return the size of the L2 cache.
171  static inline uint L2Data() { return s_L2Data; }
172  //! Return the size of the L3 cache.
173  static inline uint L3Data() { return s_L3Data; }
175  static inline ushort L1DataLineSize() { return s_L1DataLineSize; }
176  static inline ushort L2DataLineSize() { return s_L2DataLineSize; }
177  static inline ushort L3DataLineSize() { return s_L3DataLineSize; }
178  static inline uint L1Associativity() { return s_L1Associativity; }
179  static inline uint L2Associativity() { return s_L2Associativity; }
180  static inline uint L3Associativity() { return s_L3Associativity; }
181  static inline ushort prefetch() { return s_prefetch; }
182 
183  private:
184  static void interpret(uchar byte, bool *checkLeaf4);
185 
186  static uint s_ecx0;
193  static uint s_L1Data;
194  static uint s_L2Data;
195  static uint s_L3Data;
209  static bool s_noL2orL3;
210 };
211 } // namespace Vc
212 } // namespace ROOT
213 
214 #endif // CPUID_H
static uint s_processorFeaturesD
Definition: cpuid.h:189
static bool hasMmx()
Return whether the CPU supports MMX.
Definition: cpuid.h:146
static bool hasSmx()
Return whether the CPU supports the Safer Mode Extensions.
Definition: cpuid.h:87
static uint s_logicalProcessors
Definition: cpuid.h:187
static ushort L2DataLineSize()
Definition: cpuid.h:176
static bool hasXop()
Return whether the CPU supports the XOP instructions.
Definition: cpuid.h:159
static uint processorModel()
Return the model number of the processor (vendor dependent).
Definition: cpuid.h:71
static bool hasClfsh()
Return whether the CPU supports the CLFLUSH instruction.
Definition: cpuid.h:142
static uint s_L1Data
Definition: cpuid.h:193
static bool hasCx8()
Return whether the CPU supports the CMPXCHG8B instruction.
Definition: cpuid.h:136
static bool hasHtt()
Definition: cpuid.h:151
static ushort s_L3DataLineSize
Definition: cpuid.h:199
static uint s_L3Data
Definition: cpuid.h:195
static bool s_noL2orL3
Definition: cpuid.h:209
static bool hasFma()
Return whether the CPU supports FMA extensions using YMM state.
Definition: cpuid.h:95
static bool has3DNowExt()
Definition: cpuid.h:165
static uint processorFamily()
Return the family number of the processor (vendor dependent).
Definition: cpuid.h:69
static uint s_processorFeatures8C
Definition: cpuid.h:190
static ushort prefetch()
Definition: cpuid.h:181
static uchar s_cacheLineSize
Definition: cpuid.h:205
static uint s_L1Instruction
Definition: cpuid.h:192
static uint s_L1Associativity
Definition: cpuid.h:200
static uint L2Associativity()
Definition: cpuid.h:179
static ushort s_L1InstructionLineSize
Definition: cpuid.h:196
static bool hasPse()
Return whether the CPU contains Page Size Extensions.
Definition: cpuid.h:128
unsigned short ushort
Definition: cpuid.h:45
static uint s_L2Associativity
Definition: cpuid.h:201
static bool hasAes()
Return whether the CPU supports the AESNI instructions.
Definition: cpuid.h:112
static void init()
Reads the CPU capabilities and stores them for faster subsequent access.
Definition: cpuid.cpp:120
static uint L1Associativity()
Definition: cpuid.h:178
static bool isIntel()
Return whether the CPU vendor is Intel.
Definition: cpuid.h:77
static bool hasAmdPrefetch()
Return whether the CPU supports the AMD prefetchw instruction.
Definition: cpuid.h:157
static bool hasCmov()
Return whether the CPU supports CMOV instructions.
Definition: cpuid.h:140
static bool hasDe()
Return whether the CPU contains Debugging Extensions.
Definition: cpuid.h:126
static bool hasMisAlignSse()
Return whether the CPU supports misaligned SSE instructions.
Definition: cpuid.h:155
static bool hasFma4()
Return whether the CPU supports the FMA4 instructions.
Definition: cpuid.h:161
static void interpret(uchar byte, bool *checkLeaf4)
Definition: cpuid.cpp:289
static ushort s_prefetch
Definition: cpuid.h:203
static uint s_processorFeaturesC
Definition: cpuid.h:188
static bool hasPclmulqdq()
Return whether the CPU supports the PCLMULQDQ instruction.
Definition: cpuid.h:81
static uint L1Data()
Return the size of the L1 data cache.
Definition: cpuid.h:169
static bool hasSse42()
Return whether the CPU supports SSE 4.2.
Definition: cpuid.h:105
static uint L1Instruction()
Return the size of the L1 instruction cache.
Definition: cpuid.h:167
static bool hasVme()
Definition: cpuid.h:124
static ushort L1InstructionLineSize()
Definition: cpuid.h:174
static uint s_ecx0
Definition: cpuid.h:186
static bool hasCmpXchg16b()
Return whether the CPU supports CMPXCHG16B.
Definition: cpuid.h:97
static bool isAmd()
Return whether the CPU vendor is AMD.
Definition: cpuid.h:75
static uint L2Data()
Return the size of the L2 cache.
Definition: cpuid.h:171
static uint s_L3Associativity
Definition: cpuid.h:202
unsigned char byte
Definition: gifdecode.c:10
static bool hasSse2()
Return whether the CPU supports SSE2.
Definition: cpuid.h:150
static uint L3Data()
Return the size of the L3 cache.
Definition: cpuid.h:173
unsigned int uint
Definition: cpuid.h:46
static bool hasTm2()
Return whether the CPU supports Thermal Monitor 2.
Definition: cpuid.h:91
static uchar s_processorModel
Definition: cpuid.h:206
static bool hasSse41()
Return whether the CPU supports SSE 4.1.
Definition: cpuid.h:103
static uint s_processorFeatures8D
Definition: cpuid.h:191
static bool hasAcpi()
Return whether the CPU supports ACPI.
Definition: cpuid.h:144
static bool hasOsxsave()
Return whether the CPU and OS support the XSETBV/XGETBV instructions.
Definition: cpuid.h:115
static bool hasMovbe()
Return whether the CPU supports the MOVBE instruction.
Definition: cpuid.h:107
static uint s_L2Data
Definition: cpuid.h:194
static ushort L3DataLineSize()
Definition: cpuid.h:177
static bool hasEist()
Return whether the CPU supports the Enhanced Intel SpeedStep technology.
Definition: cpuid.h:89
static bool hasFpu()
Return whether the CPU contains an x87 FPU.
Definition: cpuid.h:123
static bool hasMonitor()
Return whether the CPU supports the MONITOR/MWAIT instructions.
Definition: cpuid.h:83
static ProcessorType processorType()
Return the ProcessorType.
Definition: cpuid.h:67
static uint logicalProcessors()
Return the number of logical processors.
Definition: cpuid.h:73
static bool hasVmx()
Return whether the CPU supports the Virtual Machine Extensions.
Definition: cpuid.h:85
static bool hasSse()
Return whether the CPU supports SSE.
Definition: cpuid.h:148
static bool hasF16c()
Return whether the CPU supports 16-bit floating-point conversion instructions.
Definition: cpuid.h:119
static bool hasRdrand()
Return whether the CPU supports the RDRAND instruction.
Definition: cpuid.h:121
This class is available for x86 / AMD64 systems to read and interpret information about the CPU's cap...
Definition: cpuid.h:42
static ushort s_L2DataLineSize
Definition: cpuid.h:198
static bool hasSse4a()
Return whether the CPU supports SSE4a.
Definition: cpuid.h:153
static bool hasPopcnt()
Return whether the CPU supports the POPCNT instruction.
Definition: cpuid.h:109
static bool hasSse3()
Return whether the CPU supports SSE3.
Definition: cpuid.h:79
unsigned char uchar
Definition: cpuid.h:44
static ushort cacheLineSize()
Return the cache line size in bits.
Definition: cpuid.h:65
static bool hasMsr()
Return whether the CPU supports the Model Specific Registers instructions.
Definition: cpuid.h:132
static bool hasRdtscp()
Return whether the CPU supports the RDTSCP instruction.
Definition: cpuid.h:163
static uint L3Associativity()
Definition: cpuid.h:180
static ushort L1DataLineSize()
Definition: cpuid.h:175
static bool hasPae()
Return whether the CPU supports the Physical Address Extension.
Definition: cpuid.h:134
static ushort s_L1DataLineSize
Definition: cpuid.h:197
static bool hasDca()
Return whether the CPU supports Direct Cache Access: prefetch data from a memory mapped device...
Definition: cpuid.h:101
static bool hasTsc()
Return whether the CPU supports the RDTSC instruction.
Definition: cpuid.h:130
static ProcessorType s_processorType
Definition: cpuid.h:208
static bool hasSsse3()
Return whether the CPU supports SSSE3.
Definition: cpuid.h:93
static bool hasMtrr()
Return whether the CPU supports Memory Type Range Registers.
Definition: cpuid.h:138
static bool hasAvx()
Return whether the CPU supports AVX.
Definition: cpuid.h:117
static uchar s_processorFamily
Definition: cpuid.h:207
static bool hasPdcm()
Return whether the CPU supports the Perfmon and Debug Capability.
Definition: cpuid.h:99
static bool has3DNow()
Definition: cpuid.h:164
static uchar s_brandIndex
Definition: cpuid.h:204